1. Field of the Invention
The present invention relates to a solid-state imaging device that includes a SGT (surrounding gate transistor) in which a channel region is formed in a semiconductor having an island-shaped semiconductor structure and to a solid-state imaging device that has pixels and a drive output circuit.
2. Description of the Related Art
Currently, CMOS solid-state imaging devices are widely used in video cameras, still cameras, etc. These solid-state imaging devices are constituted by pixels and a drive output circuit connected to the pixel. Improvements of performances of solid-state imaging devices, such as increasing the pixel density, increasing the resolution, decreasing mixing of colors in color imaging, and increasing the sensitivity, have always been demanded. To meet this demand, in order to increase resolution of solid-state imaging devices, technical innovations are achieved by increasing the pixel density.
A solid-state imaging device according to a known example is shown in FIGS. 8A to 8D.
FIG. 8A is a cross-sectional structural diagram of a solid-state imaging device of a known example, in which one pixel is constituted by one island-shaped semiconductor 100 (for example, refer to International Publication No. 2009/034623).
As shown in FIG. 8A, in this island-shaped semiconductor 100 constituting the pixel, a signal line N+ region 102 (hereinafter, an “N+ region” means a semiconductor region containing a donor impurity in large amounts) is formed on a substrate 101. A P region 103 (hereinafter a semiconductor region containing an acceptor impurity is referred to as a “P region”) is formed on the signal line N+ region 102, an insulating layer 104 is formed on an outer peripheral portion of the P region 103, and a gate conductor layer 105 is formed so that the insulating layer 104 is interposed. An N region (hereinafter a semiconductor region containing a donor impurity is referred to as an “N region”) 106 is formed in an outer peripheral portion of the P region 103 at a position above the gate conductor layer 105. A P+ region (hereinafter, a semiconductor region containing an acceptor impurity in a large amount is referred to as a “P+ region”) 107 is formed on the N region 106 and the P region 103 and in the upper portion of the island-shaped semiconductor 100. The P+ region 107 is connected to a pixel selection line conductor layer 108. The insulating layer 104 is formed so as to be continuous and surrounds the outer peripheral portion of the island-shaped semiconductor 100. Similarly, the gate conductor layer 105 is also formed so as to be continuous and surrounds the outer peripheral portion of the island-shaped semiconductor 100.
In this solid-state imaging device, incoming light is applied from the P+ region 107 side at the top surface of the island-shaped semiconductor 100. A photodiode region constituted by the P region 103 and the N region 106 is formed inside the island-shaped semiconductor 100, and signal charges (free electrons here) are generated in a photoelectric conversion region in the photodiode region by application of light. The signal charges are accumulated in the N region 106 of the photodiode region. In the island-shaped semiconductor 100, a junction transistor that uses the N region 106 as a gate, the P+ region 107 as a source, and the P region 103 near the signal line N+ region 102 as a drain is constructed. A drain-source current (output signal) of the junction transistor changes in response to the signal charge amount accumulated in the N region 106, is output from the signal line N+ region 102 to outside, and is read out. Moreover, in the island-shaped semiconductor 100, a reset MOS transistor that uses the N region 106 of the photodiode region as a source, the gate conductor layer 105 as a reset gate, the signal line N+ region 102 as a drain, and the P region 103 between the N region 106 and the signal line N+ region 102 as a channel is formed (hereinafter, this gate conductor layer is referred to as “reset gate conductor layer”). The signal charges accumulated in the N region 106 are discharged to the signal line N+ region 102 when a plus ON voltage is applied to the reset gate conductor layer 105 of the reset MOS transistor.
Imaging operation of this solid-state imaging device is constituted by the following operations. That is, the imaging operation is constituted by a signal charge accumulating operation of accumulating signal charges, which are generated in a photoelectric conversion region (photodiode region) due to application of a light beam entering from the top surface of the island-shaped semiconductor 100, in the N region 106 while a ground voltage (0 V) is being applied to the signal line N+ region 102, the reset gate conductor layer 105, and the P+ region 107; signal charge read-out operation of reading out, as a signal current, a source-drain current of a junction transistor modulated by a potential of the N region 106 changing in response to the accumulated signal charge amount while a ground voltage is being applied to the signal line N+ region 102 and the reset gate conductor layer 105 and a plus voltage is being applied to the P+ region 107; and a reset operation of discharging the signal charges accumulated in the N region 106 to the signal line N+ region 102 while a ground voltage is being applied to the P+ region 107 and a plus voltage is being applied to the gate conductor layer 105 and the signal line N+ region 102 after the signal charge read-out operation.
FIG. 8B is a schematic plan view of a solid-state imaging device that has a drive output circuit around a pixel region in which island-shaped semiconductors P11 to P33 (corresponding to the island-shaped semiconductor 100 in FIG. 8A) constituting pixels are arranged in a two-dimensional array (for example, refer to Japanese Unexamined Patent Application Publication No. 2009-182317).
As shown in FIG. 8B, the island-shaped semiconductors P11 to P33 constituting the pixels are formed on signal line N+ regions 102a, 102b, and 102c (corresponding to 102 in FIG. 8A). Pixel selection line conductor layers 108a, 108b, and 108c (corresponding to 108 in FIG. 8A) are formed for horizontal rows of the pixel island-shaped semiconductors P11 to P33 so as to be connected, and are connected to a pixel selection line vertical scanning circuit 110 provided near the pixel region. Similarly, reset gate conductor layers 105a, 105b, and 105c (corresponding to the gate conductor layer 105 in FIG. 8A) are formed for horizontal rows of the island-shaped semiconductors P11 to P33 so as to be connected, and are connected to a reset line vertical scanning circuit 112 provided near the pixel region. The reset line vertical scanning circuit 112 is constituted by CMOS inverter circuits 113a, 113b, and 113c constituted by SGTs connected to the reset gate conductor layers 105a, 105b, and 105c and a shift register 114 connected to the CMOS inverter circuits 113a, 113b, and 113c. The CMOS inverter circuits 113a, 113b, and 113c are configured such that two P channel SGTs and one N channel SGT are used. When a low-level voltage is applied from the shift register 114 to input terminals of the CMOS inverter circuits 113a, 113b, and 113c, a reset ON voltage VRH is applied from the output terminal to the reset gate conductor layers 105a, 105b, and 105c; in contrast, when a high-level voltage is applied, a reset OFF voltage VRL is applied from the output terminal to the reset gate conductor layers 105a, 105b, and 105c. Lower portions of the signal line N+ regions 102a, 102b, and 102c are connected to switch SGTs 115a, 115b, and 115c, and the gates of the switch SGTs 115a, 115b, and 115c are connected to a signal line horizontal scanning circuit 116. The drains of the switch SGTs 115a, 115b, and 115c are connected to an output circuit 117. Switch circuits 118a, 118b, and 118c to which a ground voltage (0 V) is applied during the signal charge accumulating operation, floating is applied during the signal charge read-out operation, and a reset voltage VRD is applied during the signal charge discharge operation are formed so as to be connected to upper portions of the signal line N+ regions 102a, 102b, and 102c. 
Here, SGT (surrounding gate transistor) refers to a transistor having a structure in which a gate conductor layer is formed on the outer periphery of a silicon pillar with a gate insulating layer therebetween.
The signal charge accumulating operation is carried out in a state in which an OFF voltage is applied from the signal line horizontal scanning circuit 116 to the gates of the switch SGTs 115a, 115b, and 115c and the switch circuits 118a, 118b, and 118c are switched to the ground voltage side so that the signal line N+ regions 102a, 102b, and 102c are at the ground voltage, in a state in which a reset OFF voltage VRL is applied to the reset gate conductor layers 105a, 105b, and 105c, and in a state in which a ground voltage is applied to the pixel selection line conductor layers 108a, 108b, and 108c. 
The signal charge read-out operation is carried out when a source-drain current of the junction transistor of a pixel to be read out is captured by the output circuit 117 in a state in which a reset OFF voltage VRL is applied to the reset gate conductor layers 105a, 105b, and 105c, a high-level voltage is applied to the pixel selection line conductor layers 108a, 108b, and 108c of the pixel to be read, an ON voltage is applied to the gates of the switch SGTs 115a, 115b, and 115c connected to the signal line N+ regions 102a, 102b, and 102c of the pixel to be read, the output terminals of the switch circuits 118a, 118b, and 118c are floating, and the input terminal of the output circuit 117 is at a low-level voltage.
The signal charge discharge operation is carried out by applying a reset-ON voltage to the reset gate conductor layers 105a, 105b, and 105c connected to the island-shaped semiconductors P11 to P33 of the pixel from which the accumulated signal charges are to be removed so that the output terminals of the switch circuits 118a, 118b, and 118c are at the reset voltage VRD while all the pixel selection line conductor layers 108a, 108b, and 108c are at the ground voltage and all the switch SGTs 115a, 115b, and 115c are OFF.
FIG. 8C is a schematic plan view of a region A surrounded by two-dot chain line in FIG. 8B. The island-shaped semiconductor P11 constituting a pixel is formed on the signal line N+ region 102a, an island-shaped semiconductor 119a constituting the N channel SGT of the CMOS inverter circuit 113a is formed on a first semiconductor layer 120a, and island-shaped semiconductors 119b and 119c constituting the P-channel SGTs are formed on a second semiconductor layer 120b. A P well region 121a is formed on (overwrapping in the drawing) the first semiconductor layer 120a so as to be connected to the lower portion of the island-shaped semiconductor 119a constituting the N-channel SGT. An N well region 121b is formed on (overwrapping in the drawing) the second semiconductor layer 120b so as to be connected to lower portions of the island-shaped semiconductors 119b and 119c constituting the P-channel SGTs. The lower portion of the island-shaped semiconductor 119a constituting the N channel SGT and an N+ region 122a connected to the lower portion are formed in the P well region 121a. The lower portions of the island-shaped semiconductors 119b and 119c constituting the P channel SGT and a P+ region 122b connected to the lower portions are formed in the N well region 121b. A drain N+ region 123a of the N channel SGT is formed in the upper portion of the island-shaped semiconductor 119a for the N channel and this drain N+ region 123a is connected to a first metal wiring layer 125a (illustrated by a one-dot chain line), to which a reset OFF voltage VRL is applied, via a contact hole 124a. 
Drain P+ regions 123b and 123c of the P channel SGTs are formed in the upper portions of the island-shaped semiconductors 119b and 119c for the P channels, and these drain P+ regions 123b and 123c are connected to a first metal wiring layer 125b (illustrated by a one-dot chain line), to which a reset ON voltage VRH is applied, via contact holes 124b and 124c. The N channel SGT-P channel SGT gate conductor layer 126 is formed so as to be continuous, and this gate conductor layer 126 is connected to a first metal wiring layer 125c (illustrated by a one-dot chain line) connected to the shift register 114 via a contact hole 127a. The reset gate conductor layer 105a of the island-shaped semiconductor P11 constituting a pixel is connected to the drain P+ region 122b of the P channel SGT via a first metal wiring layer 125e (illustrated by a one-dot chain line) and contact holes 127e and 127f. The source N+ region 122b of the P channel SGT is connected to the drain N+ region 122a of the N channel SGT via the first metal wiring layer 125b (illustrated by a one-dot chain line) and contact holes 127b and 127d. The P well region 121a is connected to a second metal wiring layer 128a (illustrated by a chain line) on the first metal wiring layers 125a, 125b, 125c, 125d, and 125e via a contact hole 127c. The N well region 121b is connected to a second metal wiring layer 128b (illustrated by a chain line) on the first metal wiring layers 125a, 125b, 125c, 125d, and 125e via the contact hole 127e. 
FIG. 8D is a cross-sectional structural diagram taken along line B-B′ in FIG. 8C. The cross-sectional structure of the island-shaped semiconductor P11 constituting a pixel is the same as that shown in FIG. 8A. The signal line N+ region 102a of the pixel, the first semiconductor layer 120a, and the second semiconductor layer 120b are formed on the substrate 100 (e.g., SiO2 layer). The island-shaped semiconductor P11 constituting the pixel is formed on the signal line N+ region 102a, the island-shaped semiconductor 119a constituting an N channel SGT is formed on the first semiconductor layer 120a, and the island-shaped semiconductors 119b and 119c constituting P channel SGTs are formed on the second semiconductor layer 120b. The P well region 121a is formed in the upper portion of the first semiconductor layer 120a, and the N well region 121b is formed in the upper portion of the second semiconductor layer 120b. The source N+ region 122a is formed in the upper portion of the P well region 121a and below the island-shaped semiconductor 119a constituting the N channel SGT. The source P+ region 122b is formed in the upper portion of the N well region 121b and below the island-shaped semiconductors 119b and 119c constituting the P channel SGTs. The drain N+ region 123a is formed in the upper portion of the island-shaped semiconductor 119a constituting the N channel SGT. The drain P+ regions 123b and 123c are formed in the upper portions of the island-shaped semiconductors 119b and 119c constituting the P channel SGTs. The channel of the N channel SGT between the source and drain N+ regions 122a and 123a of the island-shaped semiconductor 119a constituting the N channel SGT is a P region 131a, and the channels of the P channel SGT between the source and drain P+ regions 122b and 123b and 123c of the island-shaped semiconductors constituting the P channel SGTs are the N regions 131b and 131c. An N channel SGT gate insulating layer 129a is formed on the outer peripheral portion of the island-shaped semiconductor 119a constituting the N channel SGT, and an insulating layer 132a is formed on the outer periphery of the first semiconductor layer 120a so as to connect to this N channel SGT gate insulating layer 129a. 
P-channel SGT gate insulating layers 129b and 129c are formed on outer peripheral portions of the island-shaped semiconductors 119a and 119c constituting the P channel SGTs, and an insulating layer 132b is formed on the outer peripheral portion of the second semiconductor layer 120b connected to the P-channel SGT gate insulating layers 129b and 129c constituting the P channel SGTs. The reset gate conductor layer 105a of the reset MOS transistor connected to the outer peripheral portion of the island-shaped semiconductor P11 constituting the pixel is connected to the first metal wiring layer 125e via the contact hole 127f, and the first metal wiring layer 125e is connected to, via the contact hole 127b, the source P+ region 122b connected to the lower portions of the island-shaped semiconductors 119b and 119c constituting the P channel SGTs. The N channel SGT-P channel SGT gate conductor layer 126 is connected between the island-shaped semiconductor 119a constituting the N channel SGT and the island-shaped semiconductors 119b and 119c constituting the P channel SGTs and to the outer peripheries of the P-channel SGT gate insulating layers 129b and 129c and is connected to, via the contact hole 127a, the first metal wiring layer 125c connected to the shift register circuit.
The drain N+ region 123a is connected to the first metal wiring layer 125a, to which a reset OFF voltage VRL is applied, via the contact hole 124a. The drain P+ regions 123b and 123c of the P channel SGTs are connected to the first metal wiring layer 125b, to which a reset ON voltage VRH is applied, via the contact holes 124b and 124c. A first interlayer insulating layer 130a, a second interlayer insulating layer 130b, a third interlayer insulating layer 130c, a fourth interlayer insulating layer 130d, and a fifth interlayer insulating layer 130e are formed on the substrate 100 and between the first semiconductor layer 120a, the second semiconductor layer 120b, the signal line N+ region 102a, the island-shaped semiconductor 119a constituting the N channel SGT, the island-shaped semiconductors 119b and 119c constituting the P channel SGTs, and the island-shaped semiconductor P11 constituting the pixel. The reset gate conductor layer 105a of the pixel is wired on the first interlayer insulating layer 130a, the P channel-N channel SGT gate conductor layer 126 is wired on the second interlayer insulating layer 130b, the pixel selection line conductor layer 108a is wired on the third interlayer insulating layer 130c, the first metal wiring layers 125a, 125b, 125c, and 125e are formed on the fourth interlayer insulating layer 130d, and the second metal wiring layer 128a connected to the P well region 121a and the second metal wiring layer 128b connected to the N well region 121b are formed on the fifth interlayer insulating layer 130e. 
As shown in the cross-sectional structural diagram of FIG. 8D, whereas the reset gate conductor layer 105a of the reset MOS transistor in the island-shaped semiconductor P11 constituting the pixel is located at the bottom portion of the island-shaped semiconductor P11 constituting the pixel, the SGT gate conductor layer 126 of the CMOS inverter circuit 113a is located at the bottom portions of the island-shaped semiconductors 119a, 119b, and 119c constituting the SGTs on the first and second semiconductor layers 120a and 120b. The photodiode region of the island-shaped semiconductor P11 constituting the pixel is required to have a height of 2.5 to 3 μm in order to efficiently absorb light incident from the upper surface of the island-shaped semiconductor P11 constituting the pixel (refer to G. Agranov, R. Mauritzson, J. Ladd, A. Dokoutchaev, X. Fan, X. Li, Z. Yin, R. Johnson, V. Lenchenkov, S. Nagaraja, W. Gazeley, J. Bai, H. Lee, Yoshinori Takizawa; “Pixel size reduction of CMOS image sensors and comparison of characteristics”, The Institute of Image Information and television Engineers (ITE) Technical Report Vol. 33, No. 38, pp. 9-12 (September 2009)).
In contrast, the height of the reset gate conductor layer 105a and the SGT gate conductor layer 126 is about 0.1 μm or may be less. Usually, semiconductor layers 120a and 120b having the same thickness as the total thickness of the signal line N+ region 102a and the island-shaped semiconductor P11 constituting the pixel are first formed in the drive output circuit region including the CMOS inverter circuit 113a, and then an island-shaped semiconductor P11 constituting the pixel and island-shaped semiconductors 119a and 119b constituting the SGTs are formed. Accordingly, a height difference substantially equal to the height of the island-shaped semiconductor P11 constituting the pixel is inevitably generated at the height-direction position of the reset gate conductor layer 105a of the island-shaped semiconductor P11 constituting the pixel and the SGT gate conductor layer 126. Since the reset gate conductor layer 105a is formed on the first interlayer insulating layer 130a and the SGT gate conductor layer 126 is formed on the second interlayer insulating layer 130b, the reset gate conductor layer 105a and the SGT gate conductor layer 126 must be formed separately. Likewise, the signal line N+ region 102a and the N+ region 122a of the N channel SGT must be formed separately. Accordingly, production of this solid-state imaging device requires a step of forming SGTs constituting the drive output circuit in addition to the step of forming the structure of the island-shaped semiconductor P11 constituting the pixel. This leads to a decrease in yield and an increase in cost of the solid-state imaging device.
In FIGS. 8C and 8D, the P well region 121a and the N well region 121b are formed on the first and second semiconductor layers 120a and 120b. Because of the presence of the P well region 121a and the N well region 121b, an electric current generated by leaking light incident on the first and second semiconductor layers 120a and 120b is prevented from flowing into the source N+ region 122a of the N channel SGT and the source P+ region 122b of the P channel SGT, thereby suppressing malfunctions of the CMOS inverter circuit 113a. Moreover, when, for example, a ground voltage is applied to the second metal wiring layers 128a and 128b connected to the P well region 121a and the N well region 121b via the contact holes 127c and 127e, the source N+ region 122a of the N channel SGT and the source P+ region 122b of the P channel SGT are separated from the electrically floating first and second semiconductor layers 120a and 120b, thereby enabling more stable operation of the CMOS inverter circuit 113a. 
The N channel and P channel SGTs are also formed in drive output circuits other than the CMOS inverter circuit 113a, i.e., the shift register 114 of the reset line vertical scanning circuit 112, the selection line vertical scanning circuit 110, the horizontal scanning circuit 116, the output circuit 117, the switch SGTs 115a, 115b, and 115c, and the switch circuits 118a, 118b, and 118c; hence, problems leading to a decrease in yield and an increase in cost of the solid-state imaging device will arise.
In the solid-state imaging device of a known example, the reset gate conductor layer 105a of the reset MOS transistor of the island-shaped semiconductor P11 constituting the pixel is in the bottom portion of the island-shaped semiconductor P11 constituting the pixel whereas the SGT gate conductor layer 126 of the drive output circuit is located on the island-shaped semiconductors 119a and 119b that constitute the SGTs on the first and second semiconductor layers 120a and 120b and lie at substantially the same height as the upper surface of the island-shaped semiconductor P11 constituting the pixel. The height difference between the gate conductor layer 105 of the reset MOS transistor and the SGT gate conductor layer 126 of the drive output circuit is as large as 2.5 to 3 μm which is required as the photodiode region of the island-shaped semiconductor P11 constituting the pixel. Moreover, the reset gate conductor layer 105a of the reset MOS transistor and the SGT gate conductor layer 126 of the drive output circuit are formed on the different interlayer insulating layers 130a and 130b. Thus, inevitably, the reset gate conductor layer 105a of the reset MOS transistor and the SGT gate conductor layer 126 of the drive output circuit must be formed separately. Similarly, the signal line N+ region 102a and the source N+ region 122a of the N channel SGT must be formed separately. Accordingly, production of the solid-state imaging device requires a step of forming SGTs in the drive output circuit in addition to the step of forming the island-shaped semiconductor P11 constituting the pixel. This leads to a decrease in yield and an increase in cost of the solid-state imaging device. To address this, a solid-state imaging device in which the island-shaped semiconductor P11 constituting the pixel and the SGTs constituting the drive output circuit are formed on the same substrate 100 and which can suppress the decrease in yield and the increase in cost is desirable.